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Runzhou Chen

Student at UCLA

University of California, Los Angeles (UCLA)

About

Runzhou Chen received his BEng in Electronic and Computer Engineering from Hong Kong University of Science and Technology (HKUST) with first class honor in July, 2021. His undergraduate research was focused on Visible Light Communication (VLC) and was done in the Optical Wireless Lab (OWL), supervised by Professor Patrick Yue. He joined University of California, Los Angeles (UCLA) in September, 2021 as a master student in Electronic and Computer Engineering. Currently he is doing research at the High Speed Electronics Lab (HSEL), supervised by Professor M. C. Frank Chang.

Runzhou Chen’s research interests include mm-wave and high frequency circuits and systems. He is working on the D-Band FMCW radar with Ph.D. students in HSEL.

Interests

  • Mm-Wave and High Frequency Circuits and Systems
  • Analog IC Design
  • Internet of Things

Education

  • Master of Science in Electronic and Computer Engineering, 2023

    University of California, Los Angeles (UCLA)

  • Bachelor of Engineering in Electronic and Computer Engineering, 2021

    Hong Kong University of Science and Technology

Publications

Camera Pose Estimation using a VLC-Modulated Single Rectangular LED for Indoor Positioning

Keywords – Cameras, Light emitting diodes, Compass, Sensors, Lighting, Shape, Real-time systems
PDF DOI

LiDR: Visible Light Communication-Assisted Dead Reckoning for Accurate Indoor Localization

Keywords – Indoor positioning, pedestrian dead reckoning (PDR), visible light communication (VLC), optical camera communication (OCC), smartphones.
PDF DOI

Research Experience

 
 
 
 
 

A 2-GHz Class-B Power Amplifier on GaN-Based HEMTs

UCLA, ECE Dept., EE 279AS Special Topics in Physical and Wave Electronics (Instructor: Professor Ethan Wang)

Sep 2022 – Dec 2022 Los Angeles, CA
Responsibilities inlcude:

  • Design a 2-GHz two stage Class-B power amplifier with optimized load and balanced architecture on GaN-based HEMT.
  • Complete the circuit design, performance optimization, layout and post-layout simulation in ADS.
  • The PA has a performance of 28-dB small-signal gain, 0.6-GHz 3-dB bandwidth, 55% PAE, 43.4-dBm P_sat, <-20dB S11/S22 and unconditionally stability.

 
 
 
 
 

135GHz BiCMOS ×15 Frequency Multiplier with High Harmonic Rejection

High Speed Electronics Lab (HSEL), UCLA

Jun 2022 – Sep 2022 Los Angeles, CA
Responsibilities inlcude:

  • Design the 135GHz ×15 Frequency Multiplier in Global Foundry 40-nm BiCMOS (tape-out by Global Foundry on Sep 2022). The frequency multiplier is expected to have 4-dB conversion gain, 6-dBm Psat and 97mW DC power.
  • Achieve high harmonic rejection (>30dB) with the help of inter-stage filtering in-stage filtering.
 
 
 
 
 

An 8-Gbps High-Speed I/O Link with Equalization and Offset Cancellation

UCLA, ECE Dept., EE 215E Signaling and Synchronization (Instructor: Professor Sudhakar Pamarti)

Mar 2022 – May 2022 Los Angeles, CA
Responsibilities inlcude:

  • Design and simulate a differential link over a given channel (based on Cadence Spectre model) while maximizing the data rate.
  • Implement the I/O equalizations including Tx pre-emphasis and Rx-CTLE based on the generic 90nm PDK. Then enable a ±50% range of programmability for the Tx pre-emphasis and a ±20mV-±2.5mV digital offset cancellation at the Rx-CTLE.
  • The link operates at 8 Gbps with an output eye-opening larger than 100mV (under SS, TT and FF conrners) and an average power of 30mW. The Tx slew rate is limited to less than Tbit/3 each.

 
 
 
 
 

A 200-GHz Broadband Power Amplifier with 2-to-1 Power Combining

UCLA, ECE Dept., EE 279AS Special Topics in Physical and Wave Electronics (Instructor: Professor Aydin Babakhani)

Mar 2022 – May 2022 Los Angeles, CA
Responsibilities inlcude:

  • Design a 200-GHz broadband power amplifier using the ADS and transistors provided in the IHP design kit.
  • Use the transmission lines with a loss of 0.4 dB per 90 degrees for the tunning and a 2-to-1 Wilkinson power divider to improve the Pout. Then run the HB simulation in ADS to verify its behavior.
  • The PA has a performance of 21-dB small-signal gain, 134-GHz 3-dB bandwidth, 12% PAE, input and output matching between 180GHz and 220GHz, 10.4-dBm P_sat, 7-dBm P_IIP3 and unconditionally stability.

 
 
 
 
 

A 5.2-GHz Direct Conversion Receiver in 90-nm CMOS

UCLA, ECE Dept. EE215C (Instructor: Professor Behzad Razavi)

Jan 2022 – Mar 2022 Los Angeles, CA
Responsibilities inlcude:

  • Design the direct conversion receiver with LNA, I/Q mixer, oscillator and frequency-division circuit on TSMC 90nm CMOS PDK.
  • Simulate the receiver’s performance (NF, IIP3, input/output resistance, LO phase noise and gain) and make adjustments on building blocks to meet the specific requirements and limitations.
  • Tune the receiver and realize the performance of 30-dB Gain, 3.5-dB NF, -10dBm IIP3 and -110-dBc/Hz LO phase noise.

 
 
 
 
 

Reconfigurable Transceiver for D-Band FMCW and Spread-Spectrum (SS) Radars

High Speed Electronics Lab (HSEL), UCLA

Dec 2021 – May 2022 Los Angeles, CA
Responsibilities inlcude:

  • Design and test the D-Band low noise amplifier (LNA) in TSMC 16-nm CMOS for the Frequency-Modulated Continuous Wave radar (planned tape-out by TSMC on April). The LNA is expected to have 10-GHz bandwidth, 20-dB gain and less than 9-dB NF.
  • Implement the novel noise-cancelling strategy for the LNA to further reduce its noise by over 3dB per stage.
  • Develop the ×8 frequency multiplier that generates the operating frequencies (144GHz) for the FMCW radar based on the 2nd to 4th harmonics of the input frequency.
 
 
 
 
 

A 28-GHz Heterodyne Receiver in 40-nm CMOS

HKUST, ECE Dept. ECE5280 (Instructor: Professor Patrick Yue)

Mar 2021 – May 2021 Hong Kong
Responsibilities inlcude:

  • Implemented the receiver building blocks in Cadence including 2-stage LNA, I/Q mixer and VGA on TSMC 40nm CMOS PDK.
  • Assembled the receiver and verified its performance (input impedance, bandwidth, gain, NF, S11, IIP3, power consumption and EVM) by the Cadence-ADS-MATLAB co-simulation platform provided by the lab.
  • Achieved the performance of 50-ohm input resistance, 500-MHz bandwidth, 29-dB Gain, -14-dB S11, 5.9-dB NF, -14.1dBm IIP3 and 60-mW Power Consumption and 10% EVM.

 
 
 
 
 

Smart Displays and Projectors with Embedded Visible Light Communication (VLC)

Optical Wireless Lab (OWL), HKUST

Sep 2020 – May 2021 Hong Kong
Responsibilities inlcude:

  • Proposed a smart display system using VLC technology for IoT application. Made use of perspective geometry and homogeneous matrix to develop a new algorithm in MATLAB and C++ for indoor positioning and Pedestrian Dead Reckoning (PDR) based on single rectangular LED. Then measured the accuracy of the algorithm and applied it to the indoor positioning for robotic vehicles.
  • Won the Silver Award for ECE Final Year Project Industry Day 2021 and contributed to two IEEE publications.

 
 
 
 
 

A Continuous-Time Low-Pass Filter for UHF RFID Applications

HKUST, ECE Dept. ECE5040 (Instructor: Professor Howard Luong)

Sep 2020 – Dec 2020 Hong Kong
Responsibilities inlcude:

  • Designed a low power 80-dB two-stage Opamp with 92-dB voltage gain, 60-degree phase margin, 600MHz unity-gain frequency and 1.38mW power consumption.
  • Implemented a continuous-time filter based on the Opamp for UHF RFID applications. The whole circuit consists of 3 parts: a gain stage, negative feedback to emulate the source resistance, and the Chebyshev type I filter stage.
  • Verified the result using Hspice, Cadence and MATLAB. Satisfied the performance requirement of 10 – 20dB passband gain, 0.1-dB passband ripple, 50dBc adjacent channel attenuation and 77KHz upper -3dB frequency.

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